The present invention relates generally to the field of integrated circuit technology. The present invention provides an improved charge pump circuit that suppresses charge sharing due to static phase error in a high speed phase locked loop circuit.
Phase locked loop circuits are well known. FIG. 1 illustrates a block diagram of a prior art frequency synthesizer charge pump phase locked loop (PLL) circuit 100. Input signal FIN is provided to input divider 110 and an external clock signal RFC from input provider 110 is provided to a first input of phase frequency detector 120. Phase frequency detector 120 provides an xe2x80x9cupxe2x80x9d signal (designated xe2x80x9cUPxe2x80x9d) and a xe2x80x9cdownxe2x80x9d signal (designated xe2x80x9cDNxe2x80x9d) to charge pump 130. As is well known in the art, the UP signal closes a switch to cause current source 140 to provide current IUP to the output line of charge pump 130. The DN signal closes a switch to cause current source 150 to draw current IDN from the output line of charge pump 130.
The output line of charge pump 130 is coupled to loop filter 160 and to voltage controlled oscillator (VCO) 170. The currents from charge pump 130 adjust the phase of the voltage controlled oscillator 170. The output signal FOUT from voltage controlled oscillator 170 is provided to feedback divider 180. An internal clock feedback signal FBC from feedback divider 180 is provided to a second input of phase frequency detector 120. Phase frequency detector 120 compares the FBC signal from feedback divider 180 with the RFC signal from input divider 110.
A charge pump PLL is a negative feedback system that insures that the phase difference as well as the frequency difference at the input of phase frequency detector 120 is near zero under steady state conditions. A PLL in such a state is said to be in a xe2x80x9clockxe2x80x9d condition or xe2x80x9clocked.xe2x80x9d The input and output frequencies are related by a fixed ratio which can be selected by choosing the values of the input divider 110 and the feedback frequency divider 180.
A charge pump PLL is typically a second order system. Therefore, any change from the steady state condition will result in a transient response that is typically characterized by the damping factor and the natural frequency of the system. The damping factor and the natural frequency of the system are dependent upon physical quantities such as the charge pump current, the effective gain of the voltage controlled oscillator 170, the parameters of loop filter 160, and properties of the phase frequency detector 120. The settling behavior of the transient response may also be governed by the comparison frequency at the input of the phase frequency detector 120.
The output of phase frequency detector 120 comprises pulses at the UP output pin and at the DN output pin such that the difference in the pulse widths of the UP signal and the DN signal is equal to the input phase difference. The UP and DN signals are provided to charge pump 130. In response, charge pump 130 dumps an equivalent charge to adjust the phase of the voltage controlled oscillator 170. In a locked state, the output of phase frequency detector 120 comprises narrow pulses of equal duration on the UP output pin and on the DN output pin. The use of narrow pulses even in the locked state prevents the formation of a dead zone for small phase differences at the input of phase frequency detector 120.
There are deviations from ideal behavior in a practical system. For example, the xe2x80x9cupxe2x80x9d current IUP and the xe2x80x9cdownxe2x80x9d current IDN in charge pump 130 are not exactly equal due to the finite output impedance of current source 140 and current source 150. There can also be delay mismatches between the UP signal and the DN signal at the output of phase frequency detector 120. Leakage in loop filter 160 may also affect the operation of the charge pump PLL system.
Because the charge pump PLL system is a negative feedback system, the PLL corrects for all the non-ideal conditions by having a small phase offset at the input of the phase frequency detector 120 of an appropriate magnitude and polarity to negate these effects. This phase difference at the input of the phase frequency detector 120 is called the xe2x80x9cstatic phase error.xe2x80x9d
FIG. 2 illustrates a circuit diagram of a charge pump circuit 130 comprising a prior art charge sharing suppression circuit 200 capable of suppressing charge sharing due to parasitic capacitances within charge pump circuit 130.
Switch S1 in charge pump circuit 130 closes when switch S1 receives an up signal. Switch S2 in charge pump circuit 130 closes when switch S2 receives a DN signal. Output line 210 of charge pump circuit 130 outputs a control voltage VCONTROL to loop filter 160 and to voltage controlled oscillator 170.
Charge sharing suppression circuit 200 comprises signal line 220 and signal line 230. A first end of signal line 220 is coupled to the output of current source 140 at node N1. A first end of signal line 230 is coupled to the input of current source 150 at node N2. A second end of signal line 220 and a second end of signal line 230 are coupled together at node N3.
A first input of amplifier 240 is coupled to output line 210. The output of amplifier 240 is coupled to node N3. The output of amplifier 240 is also coupled to a second input of amplifier 240 to place amplifier 240 in a unity gain configuration.
Switch S3 is located within signal line 220. Switch S3 closes when switch S3 receives an inverted UP signal (denoted as UPB). Switch S4 is located within signal line 230. Switch S4 closes when switch S4 receives an inverted DN signal (denoted as DNB).
The current IUP from current source 140 and the current IDN from current source 150 need to be equal. Therefore, when node N1 and node N2 are not switched to VCONTROL (i.e., when switch S1 and switch S2 are open) then node N1 and node N2 are biased by unity gain amplifier 240 because switch S3 and switch S4 are closed. This suppresses the charge sharing from parasitic capacitance on node N1 or node N2 that can cause mismatch between current source 140 and current source 150.
Prior art charge sharing suppression circuit 200 operates correctly when the PLL is locked and there is no static phase error. However, if there is any static phase error due to the difference in arrival times of the UP signal and the DN signal there will be no return path for the charge pump currents during the duration of the static phase error.
For example, consider the UP signal and the DN signal shown in FIG. 3. The DN signal arrives before the UP signal arrives. During the time of the static phase error there is a mismatch in the signals in that the DN signal is present but the UP signal is not. There is no return path for the current IUP because switch S3 is closed (by the signal UPB) while switch S4 is still open (by the absence of the signal DNB). This condition will cause node N1 to charge up to the voltage Vdd. The extra charge is redistributed on the loop filter 160 during the next comparison cycle. This leads to low frequency jitter.
A similar situation occurs when an UP signal arrives before a DN signal. During the time of the static phase error there is a mismatch in the signals in that the UP signal is present but the DN signal is not. There is no return path for the current IDN because switch S4 is closed (by the signal DNB) while switch S3 is still open (by the absence of the signal UPB). This condition will cause node N2 to charge down to the voltage Vss. The extra charge is redistributed on the loop filter 160 during the next comparison cycle. This also leads to low frequency jitter.
It would be desirable to have a charge pump circuit in a phase locked loop circuit that is capable of suppressing charge sharing due to static phase error within the charge pump circuit.
It would also be desirable to have a charge pump circuit in a phase locked loop circuit that is capable of reducing low frequency jitter at the output of the phase locked loop circuit.
It would also be desirable to have a charge pump circuit in a phase locked loop circuit that is capable of providing a return path for charge pump currents to flow during the time that static phase error exists within the charge pump circuit.
The present invention is directed to an apparatus and method for providing a charge pump circuit in a phase locked loop circuit that is capable of suppressing charge sharing due to static phase error in a high speed phase locked loop circuit.
An advantageous embodiment of the present invention is adapted for use within a charge pump circuit of the type comprising a charge sharing suppression circuit for suppressing charge sharing due to parasitic capacitances within the charge pump circuit. The charge suppression circuit of the present invention for suppressing charge sharing due to static phase error within the charge pump generally comprises a first signal line, a second signal line and a return path signal line. The first signal line is coupled to the output of an IUP current source and to the return signal path line. The first signal line comprises a first switch that closes in response to an UP signal and a second switch that closes in response to a DNB signal. The second signal line is coupled to the return signal path line and to the input of an IDN current source. The second signal line comprises a third switch that closes in response to an UPB signal and a fourth switch that closes in response to a DN signal.
The return path signal line is coupled to an output of a unity gain amplifier in the charge sharing suppression circuit for suppressing charge sharing due to parasitic capacitances within the charge pump circuit. The combination of the first and second switches in the first signal line and the third and fourth switches in the second signal line and the return path signal line provide a return path for currents that would otherwise not be able to flow during the time that the static phase error exists due to the mismatch of an UP signal and a DN signal.
It is an object of the present invention to provide an apparatus and method for providing a charge pump circuit for a phase locked loop circuit that is capable of suppressing charge sharing due to static phase error within the charge pump circuit.
It is another object of the present invention to provide an apparatus and method for providing a charge pump circuit for a phase locked loop circuit that is capable of reducing low frequency jitter at the output of the phase locked loop circuit.
It is also an object of the present invention to provide an apparatus and method for providing a charge pump circuit for a phase locked loop circuit that is capable of providing a return path for charge pump currents to flow during the time that static phase error exists within the charge pump circuit.
It is another object of the present invention to provide an apparatus and method for providing a charge pump circuit for a phase locked loop circuit that is capable of suppressing charge sharing due to static phase error within the charge pump circuit when a DN signal arrives at the charge pump circuit before an UP signal.
It is another object of the present invention to provide an apparatus and method for providing a charge pump circuit for a phase locked loop circuit that is capable of suppressing charge sharing due to static phase error within the charge pump circuit when an UP signal arrives at the charge pump circuit before a DN signal.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprisexe2x80x9d and derivatives thereof, mean inclusion without limitation, the term xe2x80x9corxe2x80x9d is inclusive, meaning xe2x80x9cand/orxe2x80x9d; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontroller,xe2x80x9d xe2x80x9cprocessor,xe2x80x9d or xe2x80x9capparatusxe2x80x9d means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior, as well as future uses of such defined words and phrases.